HD74LV74ARPEL中文资料

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HD74LV74A

Dual D–type Flip Flops with Preset and Clear

REJ03D0312–0300Z

(Previous ADE-205-244A (Z))

Rev.3.00Jun. 02, 2004

Description

The HD74LV74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The inputdata is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-speed operation issuitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends thebattery life.

Features

VCC = 2.0 V to 5.5 V operation

All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)All outputs VO (Max.) = 5.5 V (@VCC = 0 V)

Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)

Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)Ordering Information

Package TypeSOP–14 pin(JEITA)SOP–14 pin(JEDEC)TSSOP–14 pin

Package CodeFP–14DAVFP–14DNVTTP–14DV

Package

AbbreviationFPRPT

Taping Abbreviation(Quantity)EL (2,000 pcs/reel)EL (2,500 pcs/reel)ELL (2,000 pcs/reel)

Part NameHD74LV74AFPELHD74LV74ARPELHD74LV74ATELL

Note: Please consult the sales office for the above package availability.

Function Table

InputsLHLHHH

HLLHHH

XXX↑↑↓

XXXHLX

OutputsHLH*HLQ0

LHH*LH0

Note:H:High level

L:Low levelX:Immaterial

↑:Low to high transition↓:High to low transition

Q0:The level of Q immediately before the input conditions shown in the above table is determined.

1.:Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset

and Clear go HIGH simultaneously.

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