CY7C1062AV33-12BGC中文资料

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CY7C1062AV33

512K x 32 Static RAM

Features

Highspeed—tAA = 8 ns

Low active power—1080 mW (max.)

Operating voltages of 3.3 ± 0.3V 2.0V data retention

Automatic power-down when deselected TTL-compatible inputs and outputs

Easy memory expansion with CE1, CE2, and CE3 features

Available in non Pb-free 119-ball PBGA package

pins (I/O0 through I/O7), is written into the location specified onthe address pins (A0 through A18). If Byte Enable B (BB) isLOW, then data from I/O pins (I/O8 through I/O15) is written intothe location specified on the address pins (A0 through A18).Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23and I/O24 to I/O31, respectively.

CE2, and CE3(OE) LOW and Write Enable (WE) HIGH. If the first ByteEnable (BA) is LOW, then data from the memory location0 to I/O7. If ByteEnable B (BB) is LOW, then data from memory will appear onI/O8 to I/O15. Similarly, Bc and BD correspond to the third andfourth bytes. See the truth table at the back of this data sheetfor a complete description of read and write modes.

The input/output pins (I/O0 through I/O31high-impedance state when the device is deselected (CE1,CE2or CE3 HIGH), the outputs are disabled (OE HIGH), theA-Doperation (CE1, CE2, and CE3 LOW, and WE LOW).

The CY7C1062AV33 is available in a 119-ball pitch ball gridarray (PBGA) package.

Functional Description

The CY7C1062AV33 is a high-performance CMOS StaticRAM organized as 524,288 words by 32 bits.

(CE1, CE2, and CE3 LOW) and forcing the Write Enable (WE)

input LOW. If Byte Enable A (BA) is LOW, then data from I/O

Logic Block Diagram

INPUTBUFFERS

A0A1A2A3A4A5A6A7A8A9

ROW DECODER

512K x 32ARRAY

OUTPUT BUFFERS

SENSE AMPS

I/O0–I/O31

WECECE2CE3OEBABBBBD

COLUMNDECODER

Selection Guide

–8

Maximum Access TimeMaximum Operating CurrentMaximum CMOS Standby Current

Com’lInd’lCom’l/Ind’l

830030050

–101027527550

–121226026050

mAUnitnsmA

A10A11A12A13A14A15A16A17A18

CONTROL LOGIC

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