ASM5I23S08AF-2-16-SR中文资料

September 2005

rev 1.4

ASM5P23S08A

3.3V ‘SpreadTrak’ Zero Delay Buffer

General Features

Zero input - output propagation delay, adjustable by capacitive load on FBK input.

Multiple configurations - Refer “ASM5P23S08A

Configurations” Table.

Input frequency range: 15MHz to 133MHz o Output-output skew less than 200pS. o Device-device skew less than 700pS.

o Two banks of four outputs, three-stateable by two

select inputs.

Less than 200pS Cycle-to-cycle jitter

Available in 16 pin SOIC and TSSOP Packages. Advanced 0.35µ CMOS technology. Industrial temperature available. (-1, -1H, -2, -3, -4, -5H). 3.3V operation.

Multiple low-skew outputs.

The ASM5P23S08A has two banks of four outputs each, which can be controlled by the select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes.

Multiple ASM5P23S08A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700pS.

The ASM5P23S08A is available in five different configurations (Refer “ASM5P23S08A Configurations Table). The ASM5P23S08A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P23S08A-1H is the high-drive version of the -1 and the rise and fall times on this device are faster.

The ASM5P23S08A-2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The ASM5P23S08A-3 allows the user to obtain 4X and 2X frequencies on the outputs.

The ASM5P23S08A-4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications.

The ASM5P23S08A-5H is a high-drive version with REF/2 on both banks

‘SpreadTrak’.

Functional Description

ASM5P23S08A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks. It is available in a 16 pin package. The part has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 200pS.

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