MC10H210M中文资料

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MC10H210

Dual 3 Input 3 Output ORGate

Description

The MC10H210 is designed to drive up to six transmission linessimultaneously. The multiple outputs of this device also allow the wireORing of several levels of gating for minimization of gate and packagecount.

The ability to control three parallel lines with minimum propagationdelay from a single point makes the MC10H210 particularly useful inclock distribution applications where minimum clock skew is desired.

Features

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Propagation Delay Average, 1.0 ns Typical Power Dissipation, 160 mW Typical

Improved Noise Margin 150 mV (Over Operating Voltage and

Temperature Range)Voltage CompensatedMECL 10K Compatible

Pb Free Packages are Available*

LOGIC DIAGRAM

567

91011

DIP

PIN ASSIGNMENT

VCC1AOUTAOUTAOUTAINAINAINVEE

12345678

161514131211109

VCC2VCC1BOUTBOUTBOUTBINBINBIN

VCC1 = PINS 1, 15VCC2 = PIN 16VEE = PIN 8

Pin assignment is for Dual in Line Package.

For PLCC pin assignment, see the Pin Conversion Tables on page 18

of the ON Semiconductor MECL Data Book (DL122/D).

*For additional information on our Pb Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the packagedimensions section on page 3 of this data sheet.

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